SPI0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
| RXTHINTEN | Receive FIFO Threshold Interrupt Enable. |
| TXTHINTEN | Transmit FIFO Threshold Interrupt Enable. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXTIMEOUTINTEN | Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this SPI. Writing a 1 to this bit resets the SPI timeout logic. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXFLUSH | Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty. |
| TXFLUSH | Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |